A novel design for hardware interface board with reduced resource utilization

The final cost of an integrated circuit (IC) is proportional to its testing time. One the main goals test engineers when building IC solution reduce Reduction Test time achieved by multi-site where multiple ICs are tested simultaneously using automated equipment (ATE). During testing, if a certain requires abundant resources, it accomplished one set at while other remain idle, thus lengthening total In digital-analog hybrid ICs, both analog and digital tests need be performed, increasing tester resource requirement causing shortage. This paper describes hardware interface board (HIB) design for case on Teradyne’s ETS-364 ATE. HIB's allows ATE perform I<sup>2</sup>C based tests, which usually require lot utilizing only two resources measurement resource. achieves halving I2C lowering number necessary compared set-by-set testing. proposed work has up 90.625% reduction multisite single test.